Digital Pulse Processing (Open FPGA)

Field-Programmable Gate Arrays (FPGAs) are a key technology in modern scientific instrumentation, providing the high processing speed, parallel execution, and deterministic behavior required by data acquisition, digital signal processing, and real-time control systems.

Traditionally, FPGA development has been confined to specialists with expertise in Hardware Description Languages (HDLs), such as VHDL and Verilog. While these languages provide complete control over the hardware, they also require a significant learning effort and a deep understanding of digital design, making FPGA programming inaccessible to most students approaching the subject for the first time.

The experiments presented in this section offer a different educational approach. Rather than focusing on the syntax of HDL programming, they introduce the fundamental concepts of digital logic, signal processing, and hardware implementation through a series of progressive laboratory activities. Students are encouraged to reason in terms of logical functions, data flow, and parallel processing that are essential concepts that underpin FPGA design.

To support this learning process, the experiments are based on the SCI-Compiler development environment. SCI-Compiler adopts a graphical block-diagram methodology that automatically generates the FPGA firmware from the designed application. This approach significantly lowers the entry barrier to FPGA development, allowing students with little or no experience in VHDL or Verilog to design and implement real FPGA applications. By removing the complexity of traditional HDL coding, students can focus on understanding the logical structure of the system while gaining practical experience with one of the most powerful technologies used in modern instrumentation.

LED BLINKING DEMO ON DT1260 WITH SCI-COMPILER

CAEN Educational
Open FPGA

USING THE ONBOARD OSCILLOSCOPE IN SCI-COMPILER

CAEN Educational
Open FPGA

THRESHOLD DISCRIMINATOR WITH EVENT COUNTER

CAEN Educational
Open FPGA

USING PYTHON TO ACCESS THE THRESHOLD DISCRIMINATOR REGISTERS

CAEN Educational
Open FPGA

ACQUIRING AND PLOTTING WAVEFORMS

CAEN Educational
Open FPGA

THRESHOLD SCAN WITH PYTHON

CAEN Educational
Open FPGA

FPGA-BASED DWELL TIME FOR PRECISE EVENT COUNTING

CAEN Educational

Open FPGA

MEASURING TIME-OF-FLIGHT AND TIME-OVER-THRESHOLD

CAEN Educational

Open FPGA

READING AND PLOTTING TWO SPECTRA

CAEN Educational

Open FPGA

TIMESTAMP AND TIME-OVER-THRESHOLD WITH LIST DATA BUFFER

CAEN Educational

Open FPGA

PYTHON READOUT, DECODING, AND PLOTTING OF TOF AND TOT

CAEN Educational

Open FPGA

LEADING EDGE WITH HYSTERESIS, DERIVATIVE, AND TRAPEZOIDAL TRIGGER COMPARISON

CAEN Educational

Open FPGA

MEASURING SIGNAL AMPLITUDE VIA PEAK DETECTION

CAEN Educational

Open FPGA

CHARGE INTEGRATION

CAEN Educational

Open FPGA

TRAPEZOIDAL FILTERING WITH A FULLY INTEGRATED MCA IP CORE

CAEN Educational

Open FPGA

CR–RC² SHAPING AMPLIFIER

CAEN Educational

Open FPGA

IMPLEMENTING A PULSE SHAPE DISCRIMINATOR (PSD) BASED ON AMPLITUDE VS. AREA RATIO

CAEN Educational

Open FPGA

IMPLEMENTING A PULSE SHAPE DISCRIMINATOR (PSD) BASED ON RATIO BETWEEN AREAS

CAEN Educational

Open FPGA

MULTICHANNEL READOUT USING THE ROUND ROBIN ARBITER

CAEN Educational

Open FPGA

MULTICHANNEL DESIGN USING SUB-DESIGNS

CAEN Educational

Open FPGA

SUB-BLOCK INSTANCES

CAEN Educational

Open FPGA

MEMORY-MAPPED COMPONENTS IN A SUB-DESIGN

CAEN Educational

Open FPGA