Difficult Execution Time Data Analysis Radioactive Sources
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Purpose of the experiment
This experiment introduces the concept of multichannel data acquisition and shows how multiple input channels can be managed. Students learn how several channels can share the same processing and readout resources in a controlled and efficient way.

Fundamentals
In FPGA-based systems, complex designs are often created using a modular approach, where a functional block is designed once and then reused multiple times. These reusable blocks are often called sub-designs. This approach is particularly useful in multichannel systems, where the same processing chain must be applied to several input channels. Instead of designing each channel separately, a single channel architecture can be implemented and then replicated multiple times. Using sub-designs improves design organization, simplifies debugging, and makes it easier to expand the system to a larger number of channels.

Requirements
Python environment.

Carrying out the experiment

Create a new project for your DT1260 unit by clicking New Project. A firmware design is implemented starting from a single-channel processing chain, which includes the main signal processing blocks required for event detection and measurement. This single-channel architecture is then converted into a sub-design and instantiated multiple times to create a multichannel system. The outputs of the different channels are connected to shared resources such as memory buffers and readout interfaces. Input signals are provided to the board using a pulse generator connected to multiple channels. The FPGA processes the signals independently for each channel, and the measured data are then made available to the control software.

Results
The system successfully implements a multichannel acquisition architecture using replicated sub-design blocks. Each channel processes its input signal independently while sharing common readout resources. This experiment demonstrates how modular FPGA design techniques allow scalable and efficient implementation of multichannel readout systems

Top-level schematic with two sub-design channels.
Top-level schematic with two sub-design channels.